The present invention pertains to the field of phase detection circuits. More particularly, this invention relates to a phase detector that relatively accurately detects the phase difference between two input signals having different voltage swing characteristics, wherein the phase detector substantially minimizes the phase detection error arising from parasitic capacitance.
Phase detection circuits are typically used in computer systems and other electronic systems for detecting the phase difference between two input signals. For example, in a phase locked loop (xe2x80x9cPLLxe2x80x9d) system, it is frequently desirable to generate a periodic signal waveform that is in a quadrature (i.e., 90 degree) phase relationship with a reference signal. This typically requires a phase detection circuit in the PLL system to detect any departure from the desired quadrature phase relationship between the two signals. The detected departure from the desired phase relationship between the two signals is typically referred to as quadrature phase error.
When the phase detection circuit detects the quadrature phase error, the amount of the quadrature phase error is then supplied to other circuits of the PLL system. These other circuits of the PLL system then compensate for the quadrature phase error of the two signals such that the desired quadrature phase relationship between the two signals is maintained. As is known, a PLL system is typically used to maintain stable frequency and phase characteristics of an input signal.
One type of prior art phase detection circuit for detecting the quadrature phase error of two signals is an exclusive-OR gate logic circuit. The exclusive-OR gate logic circuit detects the quadrature phase error by causing its average output voltage to be proportional to the quadrature phase error.
Disadvantages are, however, associated with the prior art exclusive-OR gate type quadrature phase detector. One disadvantage is that the prior art exclusive-OR gate type quadrature phase detector typically requires that its input signals have substantially similar voltage swing characteristics. If the input signals have different voltage swings, the average output voltage of the exclusive-OR gate typically cannot properly reflect the quadrature phase error detected.
Another disadvantage associated with such a prior art detector is that the prior art detector typically cannot accurately detect the quadrature phase error. This is often due to the fact that phase detection errors typically occur in the circuit during phase detection. One contributor to the phase detection errors is the parasitic capacitance in the circuit. Because of the unpredictable nature of the parasitic capacitance, it is often relatively difficult to compensate for the phase detection errors that arise from the parasitic capacitance.
One of the objects of the present invention is to provide a phase detector that accurately detects the phase difference between two input signals having different voltage swing characteristics.
Another object of the present invention is to provide a phase detector that substantially minimizes the phase detection error induced by the parasitic capacitance.
Another object of the present invention is to provide a phase detector that minimizes the phase detection error of the circuit by compensating for the parasitic capacitance that causes the phase detection error.
A further object of the present invention is to provide a phase detector for detecting the phase difference between a full voltage swing periodic signal and a low voltage swing quasi-differential or fully differential periodic signal, and for providing compensation for phase detection errors arising from parasitic capacitance such that substantially accurate measurement of the phase difference of the two signals can be obtained.
A phase detector is described that includes a load circuit that presents a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to (1) the first and second nodes and (2) ground for detecting a phase difference between a first input signal and a second input signal. A second circuit is coupled to (1) the first and second nodes and (2) ground for detecting the phase difference between the first and second input signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second input signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second input signals and a reference signal. The first and second circuits are cross-coupled such that an error current generated by the second circuit cancels that generated by the first circuit so that the phase detector detects the phase difference between the first and second signals with minimized phase detection error.
A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit includes (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to (1) the first and second nodes and (2) ground for detecting a phase difference between a first input signal and a second input signal. The first circuit has a first transistor coupled to the first node and a third node, a second transistor coupled to the second and third nodes, and a third transistor coupled to the third node and ground via a first current source. The first transistor receives the first input signal. The second transistor receives a reference signal. The third transistor receives the second input signal. The first and second signals have different voltage swing characteristics.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.